1. Field of the Present Invention
The present invention relates generally to the manufacture of substrate wafers of the type used in producing semiconductor devices, and, in particular, to susceptors and other substrate wafer holders for use in a substrate supporting mechanism in a reaction chamber during semiconductor manufacturing processes.
2. Background
Typical wafer holders are described in U.S. Pat. Nos. 4,821,674 and 5,427,620. These wafer holders are typically used to support a single substrate wafer during various wafer processes during the manufacture of integrated circuits. Such process applications may include silicon application processes such as chemical vapor deposition (“CVD”) and physical vapor deposition (“PVD”), thermal process applications used for treatment of semiconductor wafer substrates such as rapid thermal processing (“RTP”) and high temperature etch processing, and the like.
To save process time, substrate wafers must be loaded at an elevated temperature, and when the wafers are placed on a flat, smooth, unbroken surface, the heat-related convection currents affect the ability of the substrate wafer to settle uniformly. Thus, as shown in the aforementioned patents, a series of intersecting channels is typically machined or otherwise applied to the wafer contact surface of the holder, the intent of which is to provide a free flow of gases between the substrate and holder to avoid undesired movement of the substrate during loading and unloading operations. The presence of the intersecting channels alleviates the substrate settling issue by allowing the hot gases to escape from underneath the wafer. The intersecting channels also facilitate loading the wafers using the Bernoulli principle.
The above cited patents depict a wafer holder with only a limited number of intersecting channels. However, in practice, the number of channels required is very large because of the need to maintain a uniform temperature profile over the surface of the substrate wafer which the holder supports. In addition, it is difficult to maintain the uniformity of the channeled surface, which is critical to avoiding issues such as image transfer to the process wafer. Both temperature uniformity and image transfer issues must be avoided to ensure proper electrical and physical properties of the process wafer along with any deposited coatings.
U.S. Pat. No. 5,403,401 cites a number of manufacturing issues involving wafer holders made with a substrate contact face possessing a series of underlying, intersecting channels, a typical example of which is shown in FIGS. 1A-1C. Specifically, wafer holders of this design are difficult to maintain flat during manufacture if the channels exist only on one face of the holder. After machining, these wafer holders, which are typically machined from graphite, receive a coating, such as silicon carbide (SiC), deposited by CVD at high temperatures. As the holder cools to room temperature, differential shrinkage between the holder substrate and the coating generally leads to a state of stress, wherein the coating is under compression and the substrate under tension (although this stress state may be reversed, depending upon the properties of the substrate and the coating). The amount of stress that develops is dependent in part upon the surface area. As a result, large surface area differences between the two faces of the same holder, such as those that may exist when only one face is machined, can lead to large differences in stress, which in turn cause the part to distort or warp.
To alleviate this problem, the above-cited patent suggests that similar machining detail should be added to both faces of the wafer holder in order to avoid the differences in stress and thus ensure that the part remains flat after coating. Unfortunately, adding machining detail to both sides of the wafer holder can significantly increase its manufacturing cost. Another solution cited in the above patent is to tailor the thickness of the coating so that a controlled coating differential is maintained between the two opposite faces. In principle, this is an appropriate fix; however, in practice it can be difficult to maintain a consistent coating thickness differential between faces. There is also the problem that the amount of thickness differential required is a function of the differential in coefficient of thermal expansion (“CTE”) between the holder substrate and the surface coating. Unfortunately, certain holder substrate materials, such as graphite, have CTE's which span a range, which complicates this process. For example, the range for graphite is affected by the type of coke used in its manufacture, binder levels, particle sizing, and processing temperatures.
There is also a need to minimize the total contact area between the wafer holder and substrate wafer in order to maintain a uniform temperature profile across the surface of the wafer as well as to minimize any markings to the backside of the substrate wafer. In order to minimize total contact area, the number of channels is intentionally high, which means that the grids formed at the channel intersections are kept small. It is the tops of these individual grid areas, formed by the channels, that provide support for the wafer substrate. The problem with small grids is that they are relatively weak areas of the holder surface, and thus are prone to damage. This in turn can affect the lifetime of the wafer holder if one or more grids become damaged.
One additional drawback of wafer holders having a high number of intersecting channels on one or more faces is that such wafer holders are more prone to developing pinholes in the surface coating. This will also cause the wafer holder to be rejected, since once the coating is breached, the substrate beneath the coating is exposed to the process environment. The higher occurrence of pinholes through the surface coating on parts machined with a high number of channels is due to coating thickness variations along with cleaning issues, which are more problematic at the base of the machining detail. (Pinhole formation occurs over a period of time during use of the holder. This is generally a surface erosion problem, which can be affected by cleanliness.)
One final drawback to wafer holders machined with a high number of intersecting channels is that it is often desired to machine a concave-shaped profile into the face of the holder that is in contact with the substrate wafer, particularly for large diameter wafers and/or lower temperature processes which require a higher level of temperature uniformity. The presence of a high amount of surface detail greatly increases the complexity of machining such a profile, which further adds to the cost of the part.